Projects
Selected RTL-to-GDSII work synthesis to tape-out.
SRAM Controller ASIC
45 nm · 2026Complete RTL-to-GDSII flow for an SRAM controller at 45 nm.
- Cadence Genus
- Cadence Innovus
- TCL
- Linux
ChipTop ASIC Physical Design
45 nm · 2026Top-level ASIC physical design with congestion-aware QoR iterations.
- Cadence Innovus
- Cadence Genus
- TCL
- Linux
FIFO ASIC Physical Design
45 nm · 2026Synchronous FIFO PD with MMMC timing analysis and skew-balanced CTS.
- Cadence Innovus
- Verilog
- TCL
- MMMC