Projects
45 nm · 2026

SRAM Controller ASIC

Complete RTL-to-GDSII flow for an SRAM controller at 45 nm.

github.com/Tavakalmastan/sram_controller_asic

Flow coverage

Stages executed
RTLSynthesisFloorplanPlacementCTSRoutingSTAGDSII

Overview

An end-to-end ASIC implementation of an SRAM controller built with Cadence Genus and Innovus. The design moves from synthesizable RTL to a DRC-clean GDSII layout with timing closure and power/area reports.

Highlights

  • Implemented the complete ASIC RTL-to-GDSII flow at 45 nm using Cadence Genus and Innovus.
  • Performed Synthesis, Floorplanning, Placement, CTS, Routing, STA and DRC verification with TCL-based automation.
  • Drove negative slack to timing closure and produced DRC-clean Timing, Power and Area reports.

Tools

  • Cadence Genus
  • Cadence Innovus
  • TCL
  • Linux