Experience

Where I've actually shipped silicon work.

Roles

1 entries

  1. Physical Design Intern

    Feb 2026 – May 2026

    VLSIMINDS A Division of S2C Semiconductors Pvt. Ltd. · India · On-site

    Worked through the complete ASIC RTL-to-GDSII physical design flow at 45 nm using the Cadence backend toolchain.

    • Hands-on experience with the complete ASIC RTL-to-GDSII Physical Design flow (45 nm) using Cadence Genus and Cadence Innovus.
    • Owned key backend stages: Synthesis, Floorplanning, Placement, CTS, Routing, basic STA and MMMC timing analysis.
    • Built practical skills in TCL scripting, CMOS fundamentals, timing optimization and real-time ASIC implementation workflows.