Hi, I'm
Tavakalmastan
@TavakalmastanVLSI Physical Design Engineer
I take silicon designs from RTL to GDSIIsynthesis, floorplan, placement, CTS, routing and timing closure.
I work with Cadence Genus and Cadence Innovus, drive flows with TCL, and verify with STA, MMMC and DRC sign-off. My builds ship with positive slack and zero DRC violations.
Flow I own
RTL → GDSIISelected projects
3 totalSRAM Controller ASIC
45 nm · 2026Complete RTL-to-GDSII flow for an SRAM controller at 45 nm.
- Cadence Genus
- Cadence Innovus
- TCL
- Linux
ChipTop ASIC Physical Design
45 nm · 2026Top-level ASIC physical design with congestion-aware QoR iterations.
- Cadence Innovus
- Cadence Genus
- TCL
- Linux
FIFO ASIC Physical Design
45 nm · 2026Synchronous FIFO PD with MMMC timing analysis and skew-balanced CTS.
- Cadence Innovus
- Verilog
- TCL
- MMMC
Experience
Most recentPhysical Design Intern / VLSIMINDS S2C Semiconductors
Feb–May 2026