ChipTop ASIC Physical Design
Top-level ASIC physical design with congestion-aware QoR iterations.
github.com/Tavakalmastan/Chiptop-ASIC-PDFlow coverage
Stages executedOverview
A full physical design pass on a top-level chip — floorplan, macro placement, CTS and routing — tuned across multiple iterations to improve QoR and congestion. Closes with positive timing slack and a connectivity-clean layout.
Highlights
- Full RTL-to-GDSII PD flow in Cadence Innovus and Genus, including floorplan, macro placement, CTS, routing and timing analysis.
- TCL-driven automation with congestion optimization and multiple implementation iterations to improve QoR.
- Achieved positive timing closure, zero DRC violations, and a connectivity-clean routed layout with full QoR reports.
Tools
- Cadence Innovus
- Cadence Genus
- TCL
- Linux