45 nm · 2026

FIFO ASIC Physical Design

Synchronous FIFO PD with MMMC timing analysis and skew-balanced CTS.

github.com/Tavakalmastan/fifo-asic-physical-design

Flow coverage

Stages executed

Overview

Physical design implementation of a synchronous FIFO. The flow covers floorplan through routing with MMMC timing analysis to balance setup/hold across corners, plus power and area characterization.

Highlights

Implemented the full PD flow for a synchronous FIFO in Cadence Innovus — floorplan, placement, CTS, routing and timing analysis.
Used TCL automation and MMMC timing analysis to optimize setup/hold timing, clock skew and routing quality.
Achieved a timing-clean implementation with positive setup/hold slack along with power and area analysis.

Tools

Cadence Innovus
Verilog
TCL
MMMC